Programmable logic arrays are capable of being programmed and subsequently reprogrammed to recover particular functions and operations. The programming and reprogramming is typically carried out by removing the device or even the complete package containing the device, and reprogramming the device. This has typically been done in an EPROM Programmer at a service facility, and is not done as a user capable task.
Attempts to accomplish user programmability are described, for example in U.S. Pat. Nos. 4,879,688, 4,937,864, 5,017,809, and 5,105,388, and in European Patent 361525.
U.S. Pat. No. 4,879,688 to Turner and Rutledge for In-System Programmable Logic Device describes a programmable logic device that is field programmable and configuarble, but without testing or verification of successful field programming.
U.S. Pat. No. 4,937,864 to Caseiras, Filion, and Evanitsky for Debug Routine Accessing System describes debugging routines stored on floppy disks to unlock different debugging routines.
U.S. Pat. No. 5,017,809 to Turner for Method and Apparatus for Program Verification of A Field Programmable Logic Device describes verification of the programmed device, but not the condition of individual cells.
U.S. Pat. No. 5,105,388 Itano and Shimbayashi for Programmable Logic Device Including Verify Circuit for Macro-Cell describe a programmable memory with output and feedback.
U.S. Pat. Nos. 4,672,610 to John E. Salick for Built In Self Test Input Generator for Programmable Logic Arrays, 4,768,196 to Jou for Programmable Logic Array, 4,893,311 to Craig E. Hunter et al. for CMOS Implementation of A Built In Self Test Input Generator (BISTIG), and 5,091,908 to Zorian for Built In Self Test Technique for Read-Only Memories, as well as Japanese laid open Patent Application 2-083676 (laid open Mar. 23, 1990, Application Ser. No. 2-3591988 filed Sep. 20, 1988) of Akao et al for Semiconductor Integrated Circuit for Data Processing all describe various programmable logic circuits with built in self testing capability.
However, these documents all fail to provide a combination of pre-programming and post-programming built in self testing. They do not provide the capability of testing the underlying circuit itself for defects which may not have been evident with the prior program but which can cripple the subsequent program. This is especially true of defects which may arise on erasing a previous program.
Thus, a clear need exists for a field programmable logic array having built in self test capabilities for testing the underlying circuit itself for defects which may not have been evident with the prior program but which can cripple the subsequent program.